Binary values are the paramount representation used in digital computation. Common forms of representing values are unsigned binary numbers and signed (or two's complement) binary numbers.
Unsigned binary numbers represent integer values from zero to a value which depends on the size of the operand: 2.sup.size- 1. Each of the bits, labelled from zero at the least-significant bit position to (size-1) at the most-significant bit position, in such a number indicates a weight which is 2.sup.position. The sum of each of the weights is the value of the unsigned binary number. It should be noted that the weight of the most significant bit is 2.sup.(size-1).
Signed binary numbers represent integer values from -2.sup.(size-1) to 2.sup.(size-1) -1. The value of the left-most bit (size-1) in these operands indicates the sign of the operand: 1 indicates a negative value, and 0 indicates a positive or zero value. The weight of the sign bit can be considered to be -2.sup.(size-1). The remaining bits, labelled from zero at the least-significant bit position to (size-2) at the most-significant bit position, in such a number indicates a weight which is 2.sup.position. The sum of each of the weights is the value of the unsigned binary number.
Because unsigned and signed binary numbers differ only in the weight of the most-significant bit, certain operations, such as binary add or shift left, suffice for adding both signed and unsigned binary numbers. Other operations, such as shift right, are defined differently for unsigned and signed numbers.
Some binary computer systems include an instruction for returning the bit position of the first one (1), or most significant one (1) bit, of an unsigned binary number. Such an instruction has numerous uses, including normalizing unsigned binary numbers into a form where the most significant bit is shifted into a fixed location. Because the labelling of bits varies between computer systems, the definition of this instruction varies in turn. When the labelling of bits is in the little-endian bit order (where the least-significant bit of a binary number is labelled bit position zero and the most-significant bit is labelled bit position (size-1)), the result of such an instruction is not only the bit position, but also is the base-two logarithm of the most-significant one bit. A special condition results when the operand has a zero value (where no bits of any significance are set at all), in such a case it is appropriate to produce a value outside the normal range.
The existing binary computer systems, however, require three successive instructions for returning the bit position of the first one (1), or most significant one (1) bit, of a signed binary number. For example, in the case of 64-bit operands, an execute signed shift right immediate ("E.SHR.I 63") instruction followed by an execute exclusive-or ("E.XOR") instruction are required to modify the signed binary number prior to performing an execute unsigned logarithm of most significant bit ("E.ULMSe") instruction to compute the desired bit position. Such instructions are known to those of ordinary skill in the art. The E.SHR.I 63 instruction generates a word of all ones or all zeros, depending on the sign of the operand, the E.XOR instruction exclusive-or's the value, and then the E.ULMS instruction computes the position of the most significant zero (0) bit in the event that the operand was negative. This succession of dependent instructions, relative to the operation cycle time of a 64-bit add instruction, therefore, requires three instruction cycles. It is therefore an object of the present invention to provide an instruction for computing the binary logarithm of most significant bit of a signed binary number in a single instruction cycle time.
Additionally, an operation or computation is said to overflow if the result is outside the range of values which the size of the result of the computation can represent. For example, if the result of a binary add is eight bits, an unsigned add of values 127 and 129 would produce an overflow. Some binary computer systems include instructions which check for overflow on certain computations. For example, the Hewlett-Packard PA-RISC processor includes an instruction "ADD AND TRAP ON OVERFLOW" which adds two 32-bit binary numbers and traps if a signed overflow occurs.
Execute shift left immediate and check unsigned overflow ("E.SHL.I.UO") and execute shift left and check unsigned overflow ("E.SHL.UO") instructions provide for the shifting of a value by a fixed or variable amount, respectively, while checking that the value has not shifted out a significant bit or overflow. Such an occurrence usually indicates a loss of precision by overflow of the fixed size of the operand. This shifting corresponds to a scaling of the value or a multiplication by a power of two. Such instructions are known to those of ordinary skill in the art. It is therefore a further object of the present invention to extend the foregoing instructions to signed arithmetic, in which the values represented are from -2.sup.(size-1) to 2.sup.(size-1) -1.